Delivering Excellence in I/O and ESD Design Support!

SRF Technologies, LLC

Founded in April 2006, SRF Technologies is dedicated to supplying its customers the expertise needed to develop in-house ESD and I/O capabilities not typically available to small and start-up companies in the semiconductor industry.

We specialize in both ESD diagnostic and failure-analysis support, recognizing that such efforts can take months and cost tens of thousands of dollars.  By employing SRF Technologies, our customers have dramatically improved their debug time as well as getting the right solution at the first redesign, saving both money and time to market.

Besides ESD failure analysis and diagnostic support, our primary areas of expertise lie in ESD design for RF and analog products, as well as very large and complex SoC's involving many domains (>30). 

Extensive experience in designing ESD and I/O's to not only meet ESD requirements, such as CDM (Charge-Device Model), HBM (Human Body Model), MM (Machine Model) and CDE (speculative Cable Discharge Models), IEC 61000-4-2 system ESD, but also the rigorous demands of DFM (Design for Manufacturing), SI (signal integrity) and power delivery as they become increasingly difficult problems at 65nm and below.

SRF Technologies is a valuable resource to many companies looking to address these issues in a cost effective and efficient manner.

Stephen Fairbanks, President

With nearly 18 years of experience designing systems and products to interface to each other while withstanding the rigors of ESD and EMI susceptibility, Stephen brings a unique and honed skill set that his customers can leverage.

In the semiconductor industry, he has been developing process specific I/O and ESD libraries for 18 years. Most notable were his efforts at Intel Corporation where he was the lead developer of the ESD and I/O libraries for what was then Intel's wireless, cellular and mobile computing groups.  He lead the development of IO and ESD used on the initial and many subsequent generations of the wireless components (MAC basebands and RF Front Ends) for the Intel Centrino chipsets. He was also personally responsible for the ESD development and I/O support for 3 families of cellular communications processors and 4 families of handheld applications processors. He has developed ESD process design rules, ESD libraries, and IO libraries in Logic, RF and Mixed-signal processes at the  0.25um, 0.18um, 0.13um, 90nm, 65nm, 45/40nm and 28nm processes.  Stephen is also familiar with several specialty processes, including HV BiCMOS, Flash memory, SiGe, SOI, SOS and InP.  

Apart from ESD and IO design, he has a done significant work in system design, including compliance testing to standards such as CE, UL and other international standards.